Please use this identifier to cite or link to this item:
https://dr.ddn.upes.ac.in//xmlui/handle/123456789/1882| Title: | Design, validation and FPGA implementation of multistage telecommunication networks in HDL environment |
| Authors: | Kumar, Adesh |
| Keywords: | Telecommunication Telecommunication Networks |
| Issue Date: | Feb-2014 |
| Publisher: | College of Engineering, University of Petroleum & Energy Studies |
| Citation: | Guided by : Dr.Piyush Kuchhal and Dr. Sonal Singhal |
| URI: | http://hdl.handle.net/123456789/1882 |
| Appears in Collections: | Thesis |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Adesh Kumar PhD Thesis.pdf | 7.91 MB | Adobe PDF | View/Open |
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