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Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kumar, Adesh | - |
dc.date.accessioned | 2015-03-12T11:24:39Z | - |
dc.date.available | 2015-03-12T11:24:39Z | - |
dc.date.issued | 2014-02 | - |
dc.identifier.citation | Guided by : Dr.Piyush Kuchhal and Dr. Sonal Singhal | en_US |
dc.identifier.uri | http://hdl.handle.net/123456789/1882 | - |
dc.publisher | College of Engineering, University of Petroleum & Energy Studies | en_US |
dc.subject | Telecommunication | en_US |
dc.subject | Telecommunication Networks | en_US |
dc.title | Design, validation and FPGA implementation of multistage telecommunication networks in HDL environment | en_US |
dc.type | Article | en_US |
Appears in Collections: | Thesis |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
Adesh Kumar PhD Thesis.pdf | 7.91 MB | Adobe PDF | View/Open |
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